Integrated circuit memory devices are widely used in consumer and commercial applications. As the integration density of integrated circuit memory devices continues to increase, more memory cells may be included in each memory device. This increase in the number of memory cells in an integrated circuit memory device can make the testing thereof more time consuming and complex.
FIG. 1 is a block diagram of a conventional integrated circuit memory device testing system (apparatus). As shown in FIG. 1, a pattern generator 4 outputs a test pattern that is written in a memory to be tested, also referred to as Device Under Test (DUT) 10. The pattern generator 4 also provides an address to designate a position for the test pattern. The pattern generator 4 also outputs a desired value pattern. The desired value pattern is provided to a logic comparator 3. The logic comparator 3 preferably comprises a digital comparator that compares the desired value pattern with the test pattern that is read from the DUT 10.
When the logic comparator 3 detects a defect resulting from failure of a comparison test, the results of the comparison test are written into a corresponding address of a defect interpretation memory 7. Accordingly, the defect interpretation memory 7 preferably contains the defect information at the address of a memory cell that has the defect. The defect interpretation memory preferably has the same memory cell structure as that of the DUT 10. A testing unit, also referred to as a testing Central Processing Unit (CPU) 9, generates control signals to control the logic comparator 3, the pattern generator 4 and the defect interpretation memory 7.
In order to test the DUT 10, a test pattern from the pattern generator 4 is written into the DUT 10 by designating an address, under control of the testing CPU 9. The test pattern is read from the DUT 10 and is provided to the logic comparator 3 along with the desired value pattern that is provided by the pattern generator. If these patterns are not identical, a defect is detected. The defect information is memorized at the corresponding address of the defect interpretation memory 7. After memorizing the defect information about the DUT 10, the testing CPU 9 interprets the defect in order to, for example, substitute redundant memory cells for defective memory cells.
Therefore, in conventional testing of integrated circuit memory devices, an integrated circuit memory device is tested in a time division manner, wherein comparison tests between test pattern data that is input into a memory and resultant data that is output from the memory are performed, the results of the comparison test are loaded into a defect interpretation memory and then the results of the comparison test are analyzed. Unfortunately, these conventional testing methods may be excessively time consuming. The testing time may be further exacerbated as the size of integrated circuit memory devices continues to increase.